It is well known that carrier mobility and energy gap of silicon can be changed by a mechanical stress. And, recently, the mechanical stress plays a more and more important role in influencing performance of MOSFETs. If the carrier (electrons in NMOS transistors or holes in PMOS transistors) mobility can be increased by appropriate control of the mechanical stress, the drive current can be increased. In other words, the performance of MOSFETs can be improved greatly by the mechanical stress.
Specifically, the stress liner technology is adopted to form tensile stress liners in NMOS transistors and to form compressive stress liners in PMOS transistors, which can increase the drive currents of the NMOS transistors and the PMOS transistors and increase the response speed of an integrated circuit. According to a study, the dual stress liner technology can increase the response speed of the integrated circuit by 24%.
For example, in a PMOS transistor, firstly epitaxial layers, such as SiGe epitaxial layers, are formed in the regions where source/drain regions will be formed, and then the source/drain regions are formed by doping. By forming the SiGe epitaxial layers, a compressive stress is formed because of lattice mismatch between Si and Ge, which further improves the performance of the PMOS transistor.
A method for forming a PMOS transistor with SiGe epitaxial layers formed in source/drain regions is disclosed in a prior art. The method includes: forming a gate structure on a top surface of a substrate; forming spacers on both sidewalls of the gate structure; forming openings in the substrate on both sides of the gate structure by using the spacers as a mask; forming SiGe epitaxial layers with an epitaxial forming process in the openings; and forming source/drain regions by doping the SiGe epitaxial layers.
However, in the semiconductor manufacturing process, PMOS transistors and NMOS transistors are generally formed on a same substrate. Specifically, firstly a substrate is provided, which includes PMOS gate structures and NMOS gate structures formed thereon. Afterward, spacers are formed on both sidewalls of each gate structure. The spacers round the PMOS gate structures will be used as a mask to form epitaxial layers, and the spacers round the NMOS gate structures will be used to protect the NMOS gate structures from being exposed in an environment for forming the epitaxial layers.
In the prior art, while forming the epitaxial layers, distances between two adjacent epitaxial layers can be reduced by reducing the width of the spacers, so that compressive stresses between the epitaxial layers and channel regions are increased. However, the reduction of the width of the spacers located on both sidewalls of the NMOS gate structures may impair the protective effect for the NMOS gate structures, or even cause the NMOS gate structures to be exposed in the environment for forming the epitaxial layers, which may reduce the reliability of NMOS transistors. Similarly, the problems mentioned above may exist in a process for forming epitaxial layers on both sides of the NMOS gate structure in the prior art.